• Brief overview of 3L Diamond
• Online tutorial

Features

• build applications that target a system containing multiple FPGAs.

• work in tandem with Diamond DSP to allow you to combine DSPs and FPGAs in your system.

• greatly reduce your time to market. Describe your system with the Diamond model that leads to simple and reusable designs, reducing the costs of maintenance and development.

• add your own FPGA tasks and integrate them seamlessly with other tasks in the system - even DSP tasks.

• make use of DSP versions of tasks for rapid prototyping and system verification, and then later move these processing-intensive tasks to the FPGA without changing the rest of the system.

• utilise the FPGA processing power that is available on Sundance modules by automatically integrating your FPGA tasks with the underlying firmware.

• easily communicate with other tasks. Diamond automatically adds the necessary logic to allow this and then builds a bitstream with the standard Xilinx tools. This provides the infrastructure to let you concentrate on your development.

• build state of the art systems with very high performance in very little time making use of Sundance's high-speed ADC and DAC modules that typically contain an FPGA,.

• create tasks in a verity of ways. You can write in standard VHDL or use high-level tools| such as Xilinx System Generator ® or Celoxica's DK toolset. Tasks can also be provided as standard netlist files.

• use the fine grain parallelism that FPGAs bring to your design for processing intensive tasks.

• explore simple examples that show how to create tasks that run on an FPGA. These have been specifically designed for those who are not familiar with FPGAs.

• access all the features of the FPGA directly. This allows experienced users to create tasks that can use the pins of the FPGA for absolute freedom of design.

• remain hardware independent and compatible with the latest firmware implementations from Sundance.

• reuse tasks; You can build up your own collection of tasks or use library tasks.

• create clock domains to suite your requirements.
  • Define your own clock domains.
  • Interconnect tasks from different clock domains seamlessly without user intervention.
  • Allow Diamond FPGA to ensure automatically that different clock domains are synchronized.

• automate task such as:
  • Creation of a top-level file for each FPGA in the system.
  • Creation of all the required source files such as .ucf, .xcf etc for your specific hardware.
  • Generation of firmware for the communication resources used on Sundance modules.
  • Building a project file and makefile for your project.
  • Building the bitstream for each FPGA.
  • Reporting build errors.
  • Embedding the bitstream into the output diamond application file. Greatly simplifying maintenance and distribution.

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