FPGA Frontrunner Meet and Greet

Renishaw, Wotton-Under-Edge, 29th June 2023

We attended the FPGA Front Runners event yesterday, organised by TechNES and hosted by Renishaw at their venue in Wotton-under-Edge. An excellent facility, and thanks again to Renishaw for hosting.

The focus was on “Requirements Driven Development and Verification and the Implications for Safety”.

Topics for talks were:


  • How to capture and verify requirements
  • Spec creep and implementation changes
  • How to verify and ensure these are correctly addressed
  • Verification as a review of the system
  • Implications for safety


Pete Leonard Renishaw Engineering Talk
Jon Wright GE Aerospace Navigating the Trials and Triumphs of Aircraft System Verification
Stewart Edmondson UKESF UKESF & NANO Electronics Update
Puneet Goel Coverify Systems Technology Co-verification of SoCFPGA Designs
Diarmuid Maguire Cambridge Consultants Developing ASIC Quality & Scale Designs within FPGA Timescales
Jim Lewis SynthWorks Design Inc OSVVM in a Nutshell
Nick Tudor D-Risq Ltd In Silico AI