Introducing the AMD MicroBlaze™ V processor

A Flexible and Efficient RISC-V Processor.

The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD adaptive SoCs and FPGAs. The MicroBlaze V processor is based on a 32-bit RISC-V instruction set architecture (ISA). It allows developers to leverage the open-source RISC-V software ecosystem, is hardware compatible with the classic MicroBlaze processor, and is fully integrated in the Vivado™ and Vitis™ tools design flow. The MicroBlaze V processor is designed to be highly modular with a configurable architecture suitable for embedded systems applications.

Developers can target the MicroBlaze V processor to any AMD adaptive SoC or FPGA device supported by the Vivado Design Suite at no extra cost.


  • Based on RISC-V Open-Source ISA: Backed by a comprehensive ecosystem of industry software and solutions
  • Leverage any FPGA as an Embedded System: Supports all AMD adaptive SoCs and FPGAs available in the Vivado Design Suite at no additional charge
  • Efficient Architecture: Provides three selectable configurations: microcontroller, real-time, and application processors
  • Reduce BoM Cost: Offers an extensive array of optimized IP for integrating a MicroBlaze V processor subsystem in the programmable logic

RISC-V is an open-source standard instruction set architecture (ISA) that is managed by the non-profit RISC-V Foundation. AMD has been a member since 2020.

Based on RISC-V Open-Source ISA

  • Backed by a comprehensive ecosystem of software and solutions throughout the industry
  • Enables easy hardware migration for existing MicroBlaze processor designs and software portability for RISC-V designs
  • Configurable ISA support for RV32IMAFC Base Integer Instruction Set with optional:
    • Multiplication and division (“M” extension)
    • Atomic instructions (“A” extension)
    • Floating-point (“F” extension)
    • Code compression (“C” extension)
    • Bit manipulation (“Zba”, “Zbb”, “Zbc”, “Zbs” extensions)
  • Utilizes code compression to significantly reduce code size and save design memory


Efficient Architecture at its Core

  • Offers three selectable configurations: microcontroller, real-time processor, and application processor*
  • Provides build options to optimize area and/or performance
  • Incorporates safety measures like dual-core lockstep and triple modular redundancy (TMR) for safety-critical systems


High Degree of Design Flexibility

  • Offers a fully-integrated design flow in the Vivado and Vitis tools, identical to the MicroBlaze processor design flow
  • Compatible with any AMD adaptive SoC or FPGA supported in the Vivado design tools
  • Offers a user-friendly experience with either a graphic user interface (GUI) or command line interface (CLI)
  • Reduces system component count and shortens development time with a wide range of optimized IP available to deploy an integrated
  • MicroBlaze V processor subsystem in the programable logic
General Purpose I/O Video Memory Networking
  • Multichannel DMA
  • Streaming FIFO
  • Timer / Watchdog
  • Mutex / Mailbox
  • UART
  • USB 2.0
  • SPI
  • GPIO
  • PWM
  • HDMI Camera/Display Interface
  • Video DMA
  • DDR
  • Quad SPI
  • Ethernet Subsystem
  • Controller Area Network