NOT FOR NEW DESIGNS
Model based development tool for, Parallel Application from Rapid Simulation, with powerful Hardware In the Loop (HIL) capability
PARS is a new and emerging technology for generating parallel applications that target hardware systems comprising multiple DSP and FPGAs from a single Simulink® model. There are many software in the market that target a single DSP or FPGA from a Simulink®model but so far none of them supports multiple DSPs and FPGAs.
PARS accepts a Simulink® model as input, and helps users to partition the Simulink®model into several tasks which will be placed on different processors and/or FPGAs. PARS helps users calculate the size and type of all data transfers between different tasks and then generates the C source code with all necessary inter-task/inter-processor communication functions.
With the help of Diamond it compiles, links and then configures the various generated tasks to build a single application (*.app) file suitable for downloading into the parallel processing network. All the booting and task placement information is built into the application file together with all bit streams for the FPGAs in the system.
PARS checks the Simulink® model for the presence of any possible deadlock and in the in case of any deadlock in the model, PARS tries to resolve them. In cases where the deadlock could not be resolved automatically, it will report the source of deadlock and guide user to resolve it manually.
PARS hides the complexity of any parallel application development from the user and lets the user focus on algorithm development in Simulink®. User does not need to have deep understanding of parallel processing techniques or even DSP and FPGA. All developments are model based. By using PARS even novices could generate a parallel deployable application from a single Simulink® model in less than 30 minutes. This work was originally accomplished under a US Navy contract and Sundance would like to acknowledge this support.
Ask us for the bundle price of PARS with Diamond DSP and FPGA.
There are a selection of videos on YouTube with more information about PARS.