FC-JPEG04 – JPEG compression algorithm core for FPGA

JPEG compression algorithm core for FPGA


Sundance’s FPGA implementation for a JPEG compression algorithm, the FC-JPEG04, is based on the ISO/IEC 10918-1 standard. This intellectual property core (IP core) development uses the Xilinx Virtex-II FPGA as the reference platform hardware and can be implemented on most Sundance Xilinx-based SMT platforms.

Data is fed to the FPGA through a user selected interface and is compressed by the FC-JPEG04 engine into a JPEG JFIF format. The core compresses data by leveraging configurable tables, i.e. quantization and Huffman tables and can be customized to meet end users’ architecture specifications.

The core compresses incoming data of 10 pixels of 8 bits fed to the FPGA on every cycle of a 66 MHz clock and theoretically supports speeds of500 frames per second at a resolution of 1280 x 1024. The compression ratio, depending on the quantization and Huffman tables, can vary from 0 to 100.

  • The FC-JPEG04 primary function is to apply a DCT coefficients to input data. These coefficient apply one of the 64 cosine basic functions to various spatial frequencies (8 x 8 templates) to construct the original block.
  • Each DCT coefficient is uniformly quantized with a quantization step that is taken from a user-defined quantization table of 64, 1-byte elements. The quality and compression ratio of an encoded image can be changed by selecting q-table elements (usually by scaling up or down the values of an initial q-table).
  • After Quantization, the DCT is separated into its DC and AC coefficients, These are reordered into a 1-D format using a zigzag pattern to create long runs of zero-valued coefficients.
  • The DC coefficient is directly correlated to the mean of the 8-by-8 block (upper-left corner).
  • The AC coefficients are the values of the cosine basic functions (all other values).
  • The DC coefficient is encoded using Huffman encoded 1D-DPCM.
  • The AC coefficients are encoded using Huffman coding on magnitude/runlength pairs (magnitude of a nonzero AC coefficient plus runlength of zero-valued AC coefficients preceding it).

Design Implementation

The FC-JPEG04 core is composed of 9 modules as follows:

-Make Block -DPCM RLE -DCT -Huffman -Quantization -Reorder FIFO -ZigZag -JFIF -Local Controller


JPEG architecture-1small


Modules Slices BlkRam Mult 18 x 18
Make Block 497 16 0
DCT 1940 0 26
ZigZag 627 0 0
Quantization 264 2 8
DC_EOB 83 0 0
DPCM&RLE 414 0 0
Huffman 668 9 0
Reorder 5560 16 0
JFIF 481 0 0
Controller 158 0 0
Total 10750 45 34

FC-JPEG04 Sundance – 300504