FC003-D – SATA IP-Core for Xilinx FPGAs – Dual Host

SFC003-DSATA IP-Core for Xilinx FPGAs – Dual Host

The LDS-SATA_DUAL_HOST_XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.

The LDS-SATA_DUAL_HOST_XV5 IP is compliant with Serial ATA II specification and signaling rate is 1.5Gbps and scalable to GEN 2.

The LDS-SATA_DUAL_HOST_XV5 IP is fully synchronous with system frequency (Clock_sys) at 37.5MHz in case of GEN1 speed selection and 75MHz in case of GEN 2 speed selection. The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available.

FC-003 – pb_lds_sata_dual_host_xv5_v10