Wideband Digital Down Converter core for FPGA
A Digital Down Converter performs channel access functions in digital receivers. It is used for extracting a channel (frequency band) of interest in a wideband signal. Sundance’s wideband DDC core employs a quad DDC architecture to achieve ultra high performances. The core accepts 16-bit complex data and can process a data flow up to 3GSPS. With a fully programmable architecture at all stages of the processing, this core combines flexibility and speed.
Input stage
Four 16-bit complex samples can be loaded to the core in parallel at a rate of 250MHz, thus providing an input bandwidth of 3GSPS. The input gain, implemented using multipliers, is user programmable.
NCO
The Numerically Controlled Oscillator architecture comprises four sets of sine and cosine directly applied to the mixers.
Mixer stage
The core implements four mixers in parallel in order to keep up with the input rate. FIR filters, with user-programmable filter coefficients, process the data after the mixer stage. The output of the filters can be decimated by a factor of 2, 4, … up to 16384.
Output stage
The output data format is user programmable and ranges from 16 to 24 bits. This core can be implemented in the following Virtex II, Virtex II Pro, Virtex-4, Spartan3 with the following performances:
| Device | Sustained input rate |
|---|---|
| Virtex-II | 400MSPS |
| Virtex-II Pro | 600MSPS |
| Spartan-3 | 600MSPS |
| Virtex-4 | 1000MSPS |
A fully functional VHDL testbench and MATLAB® functions are delivered along the wideband DDC core for simulation purposes and specific performance characterization.
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