Sundance <> Xilinx System Generator <> Simulink Toolbox for VHDL code generation and co-design
Xilinx System Generator for DSP is a blockset for Simulink® which allows the modelling of fixed point systems which can be transformed into VHDL and targeted at an FPGA.
SMT6041 provides additional Simulink® blocksets for VHDL code generation and co-design to support Xilinx System Generator with Sundance FPGA/DAQ modules and the following is a list of Blocks supported:
- ComPort Read and ComPort Write
- SDL Read and SDL Write
- SDB Read and SDB Write
- SHB Read and SHB Write
- ADC and DAC for Sundance boards
- Clock Generator
- ZBT RAM
Automatic generation of the bitstream is supported with the synthesis and implementation tools run from within the Simulink® environment.
SMT6041 users needs to have a hardware design knowledge as System Generator requires detailed parameters in input.
- MATLAB® 7.0 onwards
- Simulink® version that comes bundled by default with MATLAB® 7.0 onwards
- Xilinx System Generator 8.1 (for Virtex4-based FPGA modules) / 10.1 (for
Virtex5-based FPGA modules)
- Xilinx ISE Foundation version suitable to support the Xilinx® System Generator as