TULIPP (Towards Ubiquitous Low-power Image Processing Platforms) will focus on developing a reference platform for vision-based system designers that defines a set of guidelines for the selection of relevant combinations of computing and communication resources to be instantiated in the platform while minimizing energy resources and reducing development costs and time-tomarket.
By the end of the project in 2018, TULIPP expects its work to extend the peak performance per Watt of image processing applications by 4x and average performance per Watt by 10x. Beyond the official completion of the TULIPP project, it is expected that this will be extended to 100x and 200x by 2023.
“Image processing applications stretch across an increasingly broad range of industrial domains and are reaching a higher level of complexity than ever before,” said Philippe Millet of Thales Research & Technology and TULIPP’s Project Co-ordinator. “The TULIPP reference platform will give rise to significant advances in system integration, processing innovation and idle power management to cope with the challenges this presents in increasingly complex vision-based systems.”
Define a reference platform for low power image processing applications.
Reference platform instantiation through use applications (Medical imaging, Robotics imaging, Automotive)
Demonstrate and plan improvements of defined key performance indicators.
Start-up and manage an ecosystem of stakeholder to extend image processing norms.
TULIPP demo running the HIPPEROS Real-Time Operating System
In this simple demo, the Sundance EMC2-DP (equipped with a Zynq-7030) is connected to a 720p HDMI camera and an HDMI screen. The board is running the HIPPEROS Real-Time Operating System which executes a task cycling between:
A simple HDMI pass-through,
The CPU implementation of the grayscale filter (~15fps)
The FPGA accelerated implementation of the grayscale filter (~90fps)
The CPU implementation of the sobel filter (~2fps)
The FPGA accelerated implementation of the sobel filter (~90fps)
The FPGA filters have been implemented using Vivado HLS.