The HDL Zoo
These traditional HDL were notoriously difficult to debug and verify, leading to project delays and cost increases. To help with this, several higher level options now exist. These tend to be written in a different language and then, just as C is first compiled into assembly, the higher-level language is compiled into low-level HDL i.e. Verilog/ VHDL and then into a synthesizable circuit.
Over time, interest in these traditional HDL has dwindled, but remained steady for the last 8 years or so with Verilog steadily becoming the dominant classic HDL.
High-level Synthesis (HLS)
Both of the two big FPGA giants Intel and Xilinx have a HLS compiler. These tools let developers write C/C++ which is then translated into Verilog or VHDL. They also let you verify your C code before synthesis, and then again afterwards to validate it against your RTL circuit. This workflow provides an enormous productivity boost.
OpenCL can be used to execute programmes on heterogeneous compute devices. This means that code can be run on a CPU, GPU, DSP, Tensor processor or an FPGA. Typically, a host CPU will run accelerated kernels on other available compute ‘devices’ which then accelerate the compute intensive parts of an application.
Compliant OpenCL implementations are available for a wide variety of architectures and manufacturers from Altera, AMD, ARM, Creative, IBM, Imagination, Intel, Nvidia, Qualcomm, Samsung, Vivante, Xilinx, and ZiiLABS.
Bluespec is an interesting project that has spawned its own company who specialise in RISC-V cores for FPGAs, although the compiler is still open-source. Projects are written in Bluespec System Verilog (BSV) which is a rules based methodology designed to simplify concurrency. It is often found designing CPUs where concurrency between the fetch-decode-execute can be particularly troublesome. It allows the developer to write rules, rather than worry about the state of chains of FIFOs.
The downside of Bluespec is that it produces non-deterministic systems. A consequence of this is it becomes impossible to make statements like it takes x-cycles to complete the y-instruction.
In a similar way to HLS, MyHDL is compiled into Verilog or VHDL to then be implemented on an FPGA or ASIC. However, instead of being written in C/C++, MyHDL is written in python. It is free and open source and being based on python, might be a good place to start for many people.
One reason for this is the way it simplifies the use of blocking and non-blocking assignments, which can cause confusion when starting to write HDL code. For example, consider:
a <= b
b <= a
Someone with a software background would think that b is assigned to a, and then a is assigned back to b. However the <= operator is a non-blocking assignment meaning they happen concurrently, and as such, the value of a in the second line is not the same as in the first line. This is changed in MhHDL to be:
a.next = b
b.next = a
Which is easier to understand and harder to get wrong if you are new to hardware design.
This post has been a very brief guide to what’s out there in terms of HDL but is by no means exhaustive and new HDL frameworks and languages are being developed all the time. For example, ScaleHLS was published only last year.
Ultimately, the tool you choose will be determined by your background, experience, the system you are trying to develop and its purpose. But whether you are a novice, or a professional there is no excuse not to get out there and start designing hardware today!