Twelve 16-bit ADC SLB module (10MSPS)
The SMT916 is an SLB mezzanine board that incorporates twelve AD7626 ADC chips from Analog Devices (Two groups of six ADCs, Group A for the first six channels and Group B for the next six channels). Converters are 16-bit SAR (Successive Approximation Register), with a maximum throughput of 10MSPS. Analog input connectors on the board all MMCX.
ADCs will be working as two groups of 6 converters, all in ‘self-clocked’ mode. Each group will be working simultaneously. The FPGA on the SLB base module is responsible for triggering ADC conversions. The distribution of the conversion signal will be ensured by two CDCLVD2106 chips from Texas Instrument. It features low pin to pin skew (below 50ps) and low additive jitter (below 100ps).
Samples will be collected out be the FPGA using a serial LVDS link. Bits are clocked out at a speed between 250 and 300MHz. Individual state machines synchronised to the conversion signal will ensure this process. The FPGA will generate a serial clock that will be distributed among the converters (2 groups of 6) using an LVDS clock distribution chip (CDCLVD2106).
The front-end is implemented around 2 amplifiers (Analog Devices) allowing DC levels. The input impedance will be 50 Ohms. An anti-aliasing filter follows the amplifiers before signal reach the ADCs. Cut-off frequency is half of the maximum ADC sampling rate. ADCs are driven differentially.
When it comes to synchronisation among several modules, an external clock input (slave mode) and an external clock output (master mode) connectors will be added as well as a SYNC input connector to synchronise state machines between boards. An external trigger is also present on the board. All four lines are connected to an FPGA IO and protected by clamping diodes (3.3V). MMCX connectors are used.
s916