by Chris Hamblin | Jun 18, 2015 | IP Core
SATA IP-Core for Xilinx FPGAs – Single Host The LDS-SATA_HOST_XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS-SATA_HOST_XV5 IP is compliant with Serial ATA II specification and signaling rate is...
by Chris Hamblin | Jun 18, 2015 | IP Core
SATA IP-Core for Xilinx FPGAs – Dual Host The LDS-SATA_DUAL_HOST_XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS-SATA_DUAL_HOST_XV5 IP is compliant with Serial ATA II specification and signaling rate...
by Chris Hamblin | Jun 18, 2015 | IP Core
JPEG compression algorithm core for FPGA Sundance’s FPGA implementation for a JPEG compression algorithm, the FC-JPEG04, is based on the ISO/IEC 10918-1 standard. This intellectual property core (IP core) development uses the Xilinx Virtex-II FPGA as the...
by Chris Hamblin | Jun 18, 2015 | IP Core, Product Range
Listed here is a selection of IP cores that we have available four our FPGA devices. For more information on any of them, please contact us. FC-JPEG04 – JPEG compression algorithm core for FPGAJPEG compression algorithm core for FPGA Sundance's FPGA...
