by Chris Hamblin | Jun 18, 2015 | IP Core
Wideband Digital Down Converter core for FPGA A Digital Down Converter performs channel access functions in digital receivers. It is used for extracting a channel (frequency band) of interest in a wideband signal. Sundance’s wideband DDC core employs a...
by Chris Hamblin | Jun 18, 2015 | IP Core
Sundance’s new off-the-shelf IEEE-754 FFT / IFFT Floating Point core is the most efficient available in the FPGA world. Designed for high performance programmable devices from Xilinx, this FFT core performs long transforms ranging from 32 points to 64M points...
by Chris Hamblin | Jun 18, 2015 | IP Core
SATA IP-Core for Xilinx FPGAs – Single Host The LDS-SATA_HOST_XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS-SATA_HOST_XV5 IP is compliant with Serial ATA II specification and signaling rate is...
by Chris Hamblin | Jun 18, 2015 | IP Core
SATA IP-Core for Xilinx FPGAs – Dual Host The LDS-SATA_DUAL_HOST_XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS-SATA_DUAL_HOST_XV5 IP is compliant with Serial ATA II specification and signaling rate...
by Chris Hamblin | Jun 18, 2015 | IP Core
JPEG compression algorithm core for FPGA Sundance’s FPGA implementation for a JPEG compression algorithm, the FC-JPEG04, is based on the ISO/IEC 10918-1 standard. This intellectual property core (IP core) development uses the Xilinx Virtex-II FPGA as the...
by Chris Hamblin | Jun 18, 2015 | IP Core, Product Range
Listed here is a selection of IP cores that we have available four our FPGA devices. For more information on any of them, please contact us. FC-JPEG04 – JPEG compression algorithm core for FPGAJPEG compression algorithm core for FPGA Sundance's FPGA...
